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M24C16, M24C08 M24C04, M24C02, M24C01
16/8/4/2/1 Kbit Serial IC Bus EEPROM
s
Two Wire I2C Serial Interface Supports 400 kHz Protocol Single Supply Voltage: - 4.5V to 5.5V for M24Cxx - 2.5V to 5.5V for M24Cxx-W - 1.8V to 3.6V for M24Cxx-R
s
8 1
PSDIP8 (BN) 0.25 mm frame
8 1
SO8 (MN) 150 mil width
s s s s s s s s
Hardware Write Control BYTE and PAGE WRITE (up to 16 Bytes) RANDOM and SEQUENTIAL READ Modes Self-Timed Programming Cycle Automatic Address Incrementing Enhanced ESD/Latch-Up Behavior 1 Million Erase/Write Cycles (minimum) 40 Year Data Retention (minimum)
8
SBGA
1
TSSOP8 (DW) 169 mil width SBGA5 (EA) 75 mil width
DESCRIPTION These I2C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 2048/1024/512/256/128 x 8 bit (M24C16, M24C08, M24C04, M24C02, M24C01), and operate with a power supply down to 2.5 V (for the -W version of each device), and down to 1.8 V (for the -R version of each device). The M24C16, M24C08, M24C04, M24C02, M24C01 are available in Plastic Dual-in-Line, Plastic Small Outline and Thin Shrink Small Outline packages. The M24C16-R is also available in a chip-scale (SBGA) package.
Figure 1. Logic Diagram
VCC
3
Table 1. Signal Names
E0, E1, E2 SDA Chip Enable Inputs Serial Data/Address Input/ Output Serial Clock Write Control Supply Voltage Ground
E0-E2 SCL WC M24Cxx
SDA
SCL WC VCC VSS
VSS
AI02033
September 1999
1/19
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 2A. DIP Connections
M24Cxx M24Cxx - W M24Cxx - R 1 2 3 4 8 7 6 5
where xx =16/08/04/02/01
16Kb /8Kb /4Kb /2Kb /1Kb NC / NC / NC / E0 / E0 NC / NC / E1 / E1 / E1 NC / E2 / E2 / E2 / E2 VSS
Note: 1. NC = Not Connected
VCC WC SCL SDA
AI02034C
Figure 2B. SO Connections
M24Cxx M24Cxx - W M24Cxx - R 1 2 3 4 8 7 6 5
where xx =16/08/04/02/01
16Kb /8Kb /4Kb /2Kb /1Kb NC / NC / NC / E0 / E0 NC / NC / E1 / E1 / E1 NC / E2 / E2 / E2 / E2 VSS
Note: 1. NC = Not Connected
VCC WC SCL SDA
AI02035C
Figure 2C. Standard-TSSOP Connections
where xx =04/02/01 M24Cxx M24Cxx - W where xx =04/02/01 M24Cxx - R where xx =16/08/04/02/01 1 2 3 4 8 7 6 5 VCC WC SCL SDA
AI02036C
16Kb /8Kb /4Kb /2Kb /1Kb NC / NC / NC / E0 / E0 NC / NC / E1 / E1 / E1 NC / E2 / E2 / E2 / E2 VSS
Note: 1. NC = Not Connected
Figure 2D. Turned-TSSOP Connections
M24Cxx - T where xx =16/08 M24Cxx - TW where xx =16/08
Figure 2E. SBGA Connections (top view)
M24C16 - R
WC
WC VCC NC NC
AI02216C
1 2 3 4
8 7 6 5
SCL SDA VSS NC / E2 16Kb /8Kb
SCL
VCC
SDA
VSS
AI02796C
Note: 1. NC = Not Connected
2/19
M24C16, M24C08, M24C04, M24C02, M24C01
Table 2. Absolute Maximum Ratings 1
Symbol TA TSTG Parameter Ambient Operating Temperature Storage Temperature Lead Temperature during Soldering Input or Output range Supply Voltage Electrostatic Discharge Voltage (Human Body model2) PSDIP8: 10 sec SO8: 40 sec TSSOP8: t.b.c. SBGA5: t.b.c. Value -40 to 125 -65 to 150 260 215 t.b.c. t.b.c. -0.6 to 6.5 -0.3 to 6.5 4000 Unit C C
TLEAD
C
VIO VCC VESD
V V V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents. 2. MIL-STD-883C, 3015.7 (100 pF, 1500 )
These memory devices are compatible with the I2C memory standard. This is a two wire serial interface that uses a bi-directional data bus and serial clock. The memory carries a built-in 4-bit unique Device Type Identifier code (1010) in accordance with the I2C bus definition. The memory behaves as a slave device in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a START condition, generated by the bus master. The START condition is followed by a Device Select Code and RW bit (as described in Table 3), terminated by an acknowledge bit.
When writing data to the memory, the memory inserts an acknowledge bit during the 9th bit time, following the bus master's 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a STOP condition after an Ack for WRITE, and after a NoAck for READ. Power On Reset: V CC Lock-Out Write Protect In order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included. The internal reset is held active until the V CC voltage has reached the POR threshold value, and all operations are
Figure 3. Maximum R L Value versus Bus Capacitance (CBUS) for an I2C Bus
VCC 20 Maximum RP value (k) 16 RL 12 8 4 0 10 100 CBUS (pF)
AI01665
RL
SDA MASTER fc = 100kHz fc = 400kHz SCL CBUS
CBUS 1000
3/19
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 4. I2C Bus Protocol
SCL
SDA START CONDITION SDA INPUT SDA CHANGE STOP CONDITION
SCL
1
2
3
7
8
9
SDA
MSB
ACK
START CONDITION
SCL
1
2
3
7
8
9
SDA
MSB
ACK
STOP CONDITION
AI00792
disabled - the device will not respond to any command. In the same way, when V CC drops from the operating voltage, below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable and valid VCC must be applied before applying any logic signal. SIGNAL DESCRIPTION Serial Clock (SCL) The SCL input pin is used to strobe all data in and out of the memory. In applications where this line is used by slaves to synchronize the bus to a slower clock, the master must have an open drain output, and a pull-up resistor must be connected from the SCL line to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the
master has a push-pull (rather than open drain) output. Serial Data (SDA) The SDA pin is bi-directional, and is used to transfer data in or out of the memory. It is an open drain output that may be wire-OR'ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from the SDA bus to V CC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). Chip Enable (E2, E1, E0) These chip enable inputs are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code (but see the description of memory addressing, on page 6, for more details). These inputs may be driven dynamically or tied to VCC or VSS to establish the device select code (but note that the VIL and VIH levels for the inputs are CMOS compatible, not TTL compatible).
4/19
M24C16, M24C08, M24C04, M24C02, M24C01
Table 3. Device Select Code 1
Device Type Identifier b7 M24C01 Select Code M24C02 Select Code M24C04 Select Code M24C08 Select Code M24C16 Select Code 1 1 1 1 1 b6 0 0 0 0 0 b5 1 1 1 1 1 b4 0 0 0 0 0 b3 E2 E2 E2 E2 A10 Chip Enable b2 E1 E1 E1 A9 A9 b1 E0 E0 A8 A8 A8 RW b0 RW RW RW RW RW
Note: 1. The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared against the respective external pins on the memory device. 3. A10, A9 and A8 represent high significant bits of the address.
Write Control (WC) The hardware Write Control pin (WC) is useful for protecting the entire contents of the memory from inadvertent erase/write. The Write Control signal is used to enable (WC=VIL) or disable (WC=V IH) write instructions to the entire memory area. When unconnected, the WC input is internally read as VIL, and write operations are allowed. When WC=1, Device Select and Address bytes are acknowledged, Data bytes are not acknowledged. Please see the Application Note AN404 for a more detailed description of the Write Control feature. DEVICE OPERATION The memory device supports the I2C protocol. This is summarized in Figure 4, and is compared with other serial bus protocols in Application Note AN1001. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the master, and the other as the slave. A data transfer can only be initiated by the master, which will also provide the serial clock for synchronization. The memory
device is always a slave device in all communication. Start Condition START is identified by a high to low transition of the SDA line while the clock, SCL, is stable in the high state. A START condition must precede any data transfer command. The memory device continuously monitors (except during a programming cycle) the SDA and SCL lines for a START condition, and will not respond unless one is given. Stop Condition STOP is identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition terminates communication between the memory device and the bus master. A STOP condition at the end of a Read command, after (and only after) a NoAck, forces the memory device into its standby state. A STOP condition at the end of a Write command triggers the internal EEPROM write cycle. Acknowledge Bit (ACK) An acknowledge signal is used to indicate a successful byte transfer. The bus transmitter, whether it be master or slave, releases the SDA bus after sending eight bits of data. During the 9th
Table 4. Operating Modes
Mode Current Address Read Random Address Read 1 Sequential Read Byte Write Page Write
Note: 1. X = VIH or VIL.
RW bit 1 0
WC 1 X X
Bytes 1 1
Initial Sequence START, Device Select, RW = `1' START, Device Select, RW = `0', Address reSTART, Device Select, RW = `1'
X X VIL VIL 1 1 16
1 0 0
Similar to Current or Random Address Read START, Device Select, RW = `0' START, Device Select, RW = `0'
5/19
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 5. Write Mode Sequences with WC=1 (data write inhibited)
WC ACK BYTE WRITE START DEV SEL R/W ACK NO ACK DATA IN STOP ACK NO ACK DATA IN 1
BYTE ADDR
WC ACK PAGE WRITE START DEV SEL R/W NO ACK DATA IN 3
BYTE ADDR
DATA IN 2
WC (cont'd) NO ACK PAGE WRITE (cont'd) NO ACK
DATA IN N STOP
AI02803B
clock pulse period, the receiver pulls the SDA bus low to acknowledge the receipt of the eight data bits. Data Input During data input, the memory device samples the SDA bus signal on the rising edge of the clock, SCL. For correct device operation, the SDA signal must be stable during the clock low-to-high transition, and the data must change only when the SCL line is low. Memory Addressing To start communication between the bus master and the slave memory, the master must initiate a START condition. Following this, the master sends the 8-bit byte, shown in Table 3, on the SDA bus line (most significant bit first). This consists of the 7-bit Device Select Code, and the 1-bit Read/Write Designator (RW). The Device Select Code is further subdivided into: a 4-bit Device Type Identifier, and a 3-bit Chip Enable "Address" (E2, E1, E0).
6/19
To address the memory array, the 4-bit Device Type Identifier is 1010b. Up to eight memory devices can be connected on a single I2C bus. Each one is given a unique 3-bit code on its Chip Enable inputs. When the Device Select Code is received, the memory only responds if the Chip Enable Code (shown in Table 3) is the same as the pattern applied to its Chip Enable pins. Those devices with larger memory capacities (the M24C16, M24C08 and M24C04) need more address bits. E0 is not available for use on devices that need to use address line A8; E1 is not available for devices that need to use address line A9, and E2 is not available for devices that need to use address line A10 (see Figure 2A to Figure 2D and Table 3 for details). Using the E0, E1 and E2 inputs pins, up to eight M24C02 (or M24C01), four M24C04, two M24C08 or one M24C16 device can be connected to one I 2C bus. In each case, and in the hybrid cases, this gives a total memory
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 6. Write Mode Sequences with WC=0 (data write enabled)
WC ACK BYTE WRITE START DEV SEL R/W ACK DATA IN STOP ACK DATA IN 1 ACK DATA IN 2 ACK
BYTE ADDR
WC ACK PAGE WRITE START DEV SEL R/W ACK DATA IN 3
BYTE ADDR
WC (cont'd)
ACK PAGE WRITE (cont'd) DATA IN N
ACK
STOP
AI02804
capacity of 16 Kbits, 2 KBytes (except where M24C01 devices are used). The 8th bit is the RW bit. This is set to `1' for read and `0' for write operations. If a match occurs on the Device Select Code, the corresponding memory gives an acknowledgment on the SDA bus during the 9 th bit time. If the memory does not match the Device Select Code, it deselects itself from the bus, and goes into stand-by mode. There are two modes both for read and write. These are summarized in Table 4 and described later. A communication between the master and the slave is ended with a STOP condition. Write Operations Following a START condition the master sends a Device Select Code with the RW bit set to '0', as shown in Table 4. The memory acknowledges this, and waits for an address byte. The memory responds to the address byte with an acknowledge bit, and then waits for the data byte.
Writing to the memory may be inhibited if the WC input pin is taken high. Any write command with WC=1 (during a period of time from the START condition until the end of the address byte) will not modify the memory contents, and the accompanying data bytes will not be acknowledged (as shown in Figure 5). Byte Write In the Byte Write mode, after the Device Select Code and the address, the master sends one data byte. If the addressed location is write protected by the WC pin, the memory replies with a NoAck, and the location is not modified. If, instead, the WC pin has been held at 0, as shown in Figure 6, the memory replies with an Ack. The master terminates the transfer by generating a STOP condition. Page Write The Page Write mode allows up to 16 bytes to be written in a single write cycle, provided that they
7/19
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 7. Write Cycle Polling Flowchart using ACK
WRITE Cycle in Progress
START Condition DEVICE SELECT with RW = 0
NO First byte of instruction with RW = 0 already decoded by M24xxx
ACK Returned YES
NO
Next Operation is Addressing the Memory
YES
ReSTART
Send Byte Address
STOP
Proceed WRITE Operation
Proceed Random Address READ Operation
AI01847
are all located in the same 'row' in the memory: that is the most significant memory address bits are the same. If more bytes are sent than will fit up to the end of the row, a condition known as `rollover' occurs. Data starts to become overwritten, or otherwise altered. The master sends from one up to 16 bytes of data, each of which is acknowledged by the memory if the WC pin is low. If the WC pin is high, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck. After each byte is transferred, the internal byte address counter (the 4 least significant bits only) is incremented. The transfer is terminated by the master generating a STOP condition. When the master generates a STOP condition immediately after the Ack bit (in the "10 th bit" time slot), either at the end of a byte write or a page write, the internal memory write cycle is triggered.
A STOP condition at any other time does not trigger the internal write cycle. During the internal write cycle, the SDA input is disabled internally, and the device does not respond to any requests. Minimizing System Delays by Polling On ACK During the internal write cycle, the memory disconnects itself from the bus, and copies the data from its internal latches to the memory cells. The maximum write time (tw) is shown in Table 6B, but the typical time is shorter. To make use of this, an Ack polling sequence can be used by the master.
8/19
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 8. Read Mode Sequences
ACK CURRENT ADDRESS READ START DEV SEL R/W NO ACK DATA OUT STOP ACK DEV SEL * START R/W
ACK RANDOM ADDRESS READ START DEV SEL * R/W
ACK
NO ACK DATA OUT STOP NO ACK ACK
AI01942
BYTE ADDR
ACK SEQUENTIAL CURRENT READ START DEV SEL R/W
ACK
ACK
DATA OUT 1
DATA OUT N STOP
ACK SEQUENTIAL RANDOM READ START DEV SEL * R/W
ACK DEV SEL * START
ACK
BYTE ADDR
DATA OUT 1 R/W
ACK
NO ACK
DATA OUT N STOP
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1 st and 3rd bytes) must be identical.
The sequence, as shown in Figure 7, is: - Initial condition: a Write is in progress. - Step 1: the master issues a START condition followed by a Device Select Code (the first byte of the new instruction). - Step 2: if the memory is busy with the internal write cycle, no Ack will be returned and the master goes back to Step 1. If the memory has terminated the internal write cycle, it responds with an Ack, indicating that the memory is ready to receive the second part of the next instruction (the first byte of this instruction having been sent during Step 1).
Read Operations Read operations are performed independently of the state of the WC pin. Random Address Read A dummy write is performed to load the address into the address counter, as shown in Figure 8. Then, without sending a STOP condition, the master sends another START condition, and repeats the Device Select Code, with the RW bit set to `1'. The memory acknowledges this, and outputs the contents of the addressed byte. The master must not acknowledge the byte output, and terminates the transfer with a STOP condition.
9/19
M24C16, M24C08, M24C04, M24C02, M24C01
Table 5A. DC Characteristics (TA = 0 to 70 C, or -40 to 85 C; VCC = 4.5 to 5.5 V or 2.5 to 5.5 V) (TA = 0 to 70 C, or -40 to 85 C; VCC = 1.8 to 3.6 V)
Symbol ILI ILO Parameter Input Leakage Current (SCL, SDA) Output Leakage Current Test Condition 0 V VIN VCC 0 V VOUT VCC, SDA in Hi-Z VCC=5V, fc=400kHz (rise/fall time < 30ns) ICC Supply Current -W series: -R series: VCC =2.5V, fc=400kHz (rise/fall time < 30ns) VCC =1.8V, fc=400kHz (rise/fall time < 30ns) VIN = VSS or VCC , VCC = 5 V ICC1 Supply Current (Stand-by) -W series: -R series: VIL VIH VIL VIH Input Low Voltage (E0, E1, E2, SCL, SDA) Input High Voltage (E0, E1, E2, SCL, SDA) Input Low Voltage (WC) Input High Voltage (WC) IOL = 3 mA, VCC = 5 V VOL Output Low Voltage -W series: -R series:
Note: 1. This is preliminary data.
Min.
Max. 2 2 2 1 0.81 1 0.5 0.11
Unit A A mA mA mA A A A V V V V V V V
VIN = VSS or VCC , VCC = 2.5 V VIN = VSS or VCC , VCC = 1.8 V - 0.3 0.7VCC - 0.3 0.7VCC
0.3 VCC VCC+1 0.5 VCC+1 0.4 0.4 0.21
IOL = 2.1 mA, VCC = 2.5 V IOL = 0.7 mA, VCC = 1.8 V
Current Address Read The device has an internal address counter which is incremented each time a byte is read. For the Current Address Read mode, following a START condition, the master sends a Device Select Code with the RW bit set to `1'. The memory acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The master terminates the transfer with a STOP condition, as shown in Figure 8, without acknowledging the byte output. Sequential Read This mode can be initiated with either a Current Address Read or a Random Address Read. The master does acknowledge the data byte output in this case, and the memory continues to output the next byte in sequence. To terminate the stream of bytes, the master must not acknowledge the last byte output, and must generate a STOP condition. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output.
After the last memory address, the address counter `rolls-over' and the memory continues to output data from memory address 00h. Acknowledge in Read Mode In all read modes, the memory waits, after each byte read, for an acknowledgment during the 9th bit time. If the master does not pull the SDA line low during this time, the memory terminates the data transfer and switches to its stand-by state.
10/19
M24C16, M24C08, M24C04, M24C02, M24C01
Table 5B. DC Characteristics1 (TA = -40 to 125 C; VCC = 4.5 to 5.5 V)
Symbol ILI ILO ICC ICC1 VIL VIH VIL VIH VOL Parameter Input Leakage Current (SCL, SDA) Output Leakage Current Supply Current Supply Current (Stand-by) Input Low Voltage (E0, E1, E2, SCL, SDA) Input High Voltage (E0, E1, E2, SCL, SDA) Input Low Voltage (WC) Input High Voltage (WC) Output Low Voltage IOL = 3 mA, VCC = 5 V Test Condition 0 V VIN VCC 0 V VOUT VCC, SDA in Hi-Z VCC=5V, fc=400kHz (rise/fall time < 30ns) VIN = VSS or VCC , VCC = 5 V - 0.3 0.7VCC - 0.3 0.7VCC Min. Max. 2 2 3 5 0.3 VCC VCC+1 0.5 VCC+1 0.4 Unit A A mA A V V V V V
Note: 1. This is preliminary data.
Table 6A. AC Characteristics
M24C16, M24C08, M24C04, M24C02, M24C01 Symbol Alt. Parameter VCC=4.5 to 5.5 V VCC=2.5 to 5.5 V VCC=1.8 to 3.6 V TA=0 to 70C or TA=0 to 70C or TA=0 to 70C or Unit -40 to 85C -40 to 85C -40 to 85C4 Min tCH1CH2 tCL1CL2 tDH1DH2 2 tDL1DL2 2 tCHDX 1 tCHCL tDLCL tCLDX tCLCH tDXCX tCHDH tDHDL tCLQV 3 tCLQX fC tW
Note: 1. 2. 3. 4.
Max 300 300
Min
Max 300 300
Min
Max 300 300 ns ns ns ns ns ns ns s s ns ns s 900 ns ns 400 10 kHz ms
tR tF tR tF tSU:STA tHIGH tHD:STA
Clock Rise Time Clock Fall Time SDA Rise Time SDA Fall Time Clock High to Input Transition Clock Pulse Width High Input Low to Clock Low (START) 20 20 600 600 600 0 1.3 100 600 1.3 200 200
300 300
20 20 600 600 600 0 1.3 100 600 1.3
300 300
20 20 600 600 600 0 1.3 100 600 1.3
300 300
tHD:DAT Clock Low to Input Transition tLOW tSU:DAT Clock Pulse Width Low Input Transition to Clock Transition
tSU:STO Clock High to Input High (STOP) tBUF tAA tDH fSCL tWR Input High to Input Low (Bus Free) Clock Low to Data Out Valid Data Out Hold Time After Clock Low Clock Frequency Write Time
900
200 200
900
200 200
400 5
400 10
For a reSTART condition, or following a write cycle. Sampled only, not 100% tested. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. This is preliminary data.
11/19
M24C16, M24C08, M24C04, M24C02, M24C01
Table 6B. AC Characteristics4
M24C16, M24C08, M24C04, M24C02, M24C01 Symbol Alt. Parameter VCC=4.5 to 5.5 V; TA=-40 to 125C Min tCH1CH2 tCL1CL2 tDH1DH2 2 tDL1DL2 2 tCHDX 1 tCHCL tDLCL tCLDX tCLCH tDXCX tCHDH tDHDL tCLQV 3 tCLQX fC tW
Note: 1. 2. 3. 4.
Unit
Max 300 300 ns ns ns ns ns ns ns s s ns ns s 900 ns ns 400 10 kHz ms
tR tF tR tF tSU:STA tHIGH tHD:STA
Clock Rise Time Clock Fall Time SDA Rise Time SDA Fall Time Clock High to Input Transition Clock Pulse Width High Input Low to Clock Low (START) 20 20 600 600 600 0 1.3 100 600 1.3 200 200
300 300
tHD:DAT Clock Low to Input Transition tLOW tSU:DAT Clock Pulse Width Low Input Transition to Clock Transition
tSU:STO Clock High to Input High (STOP) tBUF tAA tDH fSCL tWR Input High to Input Low (Bus Free) Clock Low to Data Out Valid Data Out Hold Time After Clock Low Clock Frequency Write Time
For a reSTART condition, or following a write cycle. Sampled only, not 100% tested. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. This is preliminary data.
Table 7. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Reference Voltages 50 ns 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC
Figure 9. AC Testing Input Output Waveforms
0.8VCC 0.7VCC 0.3VCC
AI00825
0.2VCC
Table 8. Input Parameters1 (TA = 25 C, f = 400 kHz)
Symbol CIN CIN ZWCL ZWCH tNS Parameter Input Capacitance (SDA) Input Capacitance (other pins) WC Input Impedance WC Input Impedance Glitch pulse width ignored (input filter on SCL and SDA) VIN < 0.5 V VIN > 0.7VCC 5 500 100 Test Condition Min. 8 6 70 Max. pF pF k k ns Unit
Note: 1. Sampled only, not 100% tested.
12/19
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 10. AC Waveforms
tCHCL SCL tDLCL SDA IN tCHDX START CONDITION tCLDX SDA INPUT SDA CHANGE STOP & BUS FREE tDHDL tDXCX tCHDH tCLCH
SCL tCLQV SDA OUT DATA VALID tCLQX
DATA OUTPUT
SCL tW SDA IN tCHDH STOP CONDITION WRITE CYCLE tCHDX START CONDITION
AI00795B
13/19
M24C16, M24C08, M24C04, M24C02, M24C01
Table 9. Ordering Information Scheme
Example: M24C08 - T W DW 1 T
Memory Capacity 16 08 04 02 01 16 Kbit (2048 x 8) 8 Kbit (1024 x 8) 4 Kbit (512 x 8) 2 Kbit (256 x 8) 1 Kbit (128 x 8) 11 6 TSSOP Pin-Out Standard (as shown in Figure 1) for: M24C01, M24C01-W, M24C01-R, blank M24C02, M24C02-W, M24C02-R, M24C04, M24C04-W, M24C04-R, M24C08-R, M24C16-R. T Turned (as shown in Figure 2D) for M24C08-T, M24C08-TW, M24C16-T, M24C16-TW 3 T
Option Tape and Reel Packing
Temperature Range 0 C to 70 C -40 C to 85 C -40 C to 125 C
Operating Voltage blank 4.5 V to 5.5 V W R 2.5 V to 5.5 V 1.8 V to 3.6 V BN MN DW EA
Note: 1. Temperature range 1 available only on request. 2. SBGA5 package available only for the "M24C16-R EA 6 T"
Package PSDIP8 (0.25 mm frame) SO8 (150 mil width) TSSOP8 (169 mil width) SBGA52
ORDERING INFORMATION Devices are shipped from the factory with the memory content set at all `1's (FFh). The notation used for the device number is as shown in Table 9. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
14/19
M24C16, M24C08, M24C04, M24C02, M24C01
Table 10. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
mm Symb. Typ. A A1 A2 B B1 C D E E1 e1 eA eB L N 3.00 8 2.54 7.62 Min. 3.90 0.49 3.30 0.36 1.15 0.20 9.20 - 6.00 - 7.80 Max. 5.90 - 5.30 0.56 1.65 0.36 9.90 - 6.70 - - 10.00 3.80 0.118 8 0.100 0.300 Typ. Min. 0.154 0.019 0.130 0.014 0.045 0.008 0.362 - 0.236 - 0.307 Max. 0.232 - 0.209 0.022 0.065 0.014 0.390 - 0.264 - - 0.394 0.150 inches
Figure 11. PSDIP8 (BN)
A2 A1 B B1 D
N
A L eA eB C
e1
E1
1
E
PSDIP-a
Note: 1. Drawing is not to scale.
15/19
M24C16, M24C08, M24C04, M24C02, M24C01
Table 11. SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm Symb. Typ. A A1 B C D E e H h L N CP 1.27 Min. 1.35 0.10 0.33 0.19 4.80 3.80 - 5.80 0.25 0.40 0 8 0.10 Max. 1.75 0.25 0.51 0.25 5.00 4.00 - 6.20 0.50 0.90 8 0.050 Typ. Min. 0.053 0.004 0.013 0.007 0.189 0.150 - 0.228 0.010 0.016 0 8 0.004 Max. 0.069 0.010 0.020 0.010 0.197 0.157 - 0.244 0.020 0.035 8 inches
Figure 12. SO8 narrow (MN)
h x 45 A C B e D CP
N
E
1
H A1 L
SO-a
Note: 1. Drawing is not to scale.
16/19
M24C16, M24C08, M24C04, M24C02, M24C01
Table 12. TSSOP8 - 8 lead Thin Shrink Small Outline
mm Symb. Typ. A A1 A2 B C D E E1 e L N CP 0.65 0.05 0.85 0.19 0.09 2.90 6.25 4.30 - 0.50 0 8 0.08 Min. Max. 1.10 0.15 0.95 0.30 0.20 3.10 6.50 4.50 - 0.70 8 0.026 0.002 0.033 0.007 0.004 0.114 0.246 0.169 - 0.020 0 8 0.003 Typ. Min. Max. 0.043 0.006 0.037 0.012 0.008 0.122 0.256 0.177 - 0.028 8 inches
Figure 13. TSSOP8 (DW)
D
N
DIE
C
E1 E
1
N/2
A1
A A2
L
CP
B
e TSSOP
Note: 1. Drawing is not to scale.
17/19
M24C16, M24C08, M24C04, M24C02, M24C01
Table 13. SBGA5 - 8 ball Shell Ball Grid Array
mm Symb. Typ. A A1 D D1 E E1 e ball diameter N 0.430 0.180 1.900 1.190 1.750 1.070 0.800 0.350 Min. 0.380 0.150 1.870 1.160 1.725 1.040 0.770 0.320 5 Max. 0.480 0.210 1.930 1.220 1.775 1.100 0.830 0.380 Typ. 0.017 0.007 0.075 0.047 0.069 0.042 0.031 0.014 Min. 0.015 0.006 0.074 0.046 0.068 0.041 0.030 0.013 5 Max. 0.019 0.008 0.076 0.048 0.070 0.043 0.033 0.015 inches
Figure 14. SBGA5 (EA) - Underside view (ball side)
D D1
BALL "1"
E1
E
e
A
A1
SBGA-00
Note: 1. Drawing is not to scale.
18/19
M24C16, M24C08, M24C04, M24C02, M24C01
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) 1999 STMicroelectronics - All Rights Reserved The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
19/19

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